Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller
نویسندگان
چکیده
This paper investigates the behavior of a SEU tolerant 8051-like micro-controller protected by single error correction Hamming Code in the presence of multiple upsets. Single event upsets (SEUs) and multiple bit upsets (MBUs) were analyzed, since they are more likely to occur in nano-metric technologies under high-energy heavy-ions. Upsets were randomly injected in all sensitive parts of the design, such as registers, flip-flops and memory, at a random time during the micro-controller application program execution. The experiment was emulated in a Virtex FPGA platform. Results evaluate the robustness of the tolerant 8051 in a multiple upsets environment.
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